The present invention relates generally to memory circuits adapted for implementation in the form of integrated semiconductor circuit chips, and more particularly to metal oxide silicon chip memory arrays using cross-coupled sensing Metal-Oxide-Field Effect Transistors (MOSFETs) connected in a race mode between a bit line and a precharged storage capacitance.
The typical configuration of semiconductor dynamic random access memories (RAMs) is constructed from a plurality of capacitive memory cells arranged to form a memory array in which each of the individual memory cells is capable of being identified by a column (or Y) address and a row (or X) address. As a general rule, for the same number of total bits, the use of more rows and fewer columns increases the complexity of the circuit per bit (due to the need for sensing amplifiers) but decreases the response time and improved sensitivity (due to the reduction of the bit line capacitances as compared to the memory capacitances). Particular arrangements are therefore generally chosen to represent an optimum design compromise.
In any given column the memory cells are arranged in two groups to represent a pair of halves of the total memory cells in that column. Each memory cell is connected to half of a bit line which, in turn, is connected to the gate electrode of one of a cross-coupled pair of MOSFETs that form a sense amplifier circuit. The other half of the bit line is connected to the gate electrode of the other of the MOSFET pair. The sense amplifier circuit takes advantage of the incremental voltage changes on the inherent bit line half capacitances when a memory cell is read to establish a race between the two cross-coupled MOSFETs. The race provides a clear read-out signal regardless of the relative capacitances involved. Examples of such capacitive memory elements and their arrangement can be found described in U.S. Pat. Nos. 3,514,765 and 3,678,473.
Recent advances in semiconductor manufacturing have seen such capacitive memory circuits evolve from a single chip containing 2,048 bits of capacitive memory (arranged, for example, in an array containing 16 rows and 128 columns) to presently commercially available embodiments of semiconductor chips capable of storing 65,536 bits. And, there is a race toward a reliable 256K (262,144) bit memory unit on one chip. Future prospects, the 1,000,000-bit chip, are believed possible.
Notwithstanding these recent (and, according to some, spectacular) advances in semiconductor memory technology, the desire to incorporate more and more functional circuitry on each individual chip, together with the commercial realities of yield, cost, and the like, have caused the semiconductor area available for circuitry to become extremely valuable. Concomitant with semiconductor advances is the development of improved techniques of packing more and more circuitry on smaller and smaller areas of silicon. Thus, when limits in fabrication techniques are encountered, industry focus turns to more efficient circuit design to reduce the component count and, in turn, to reduce the chip area upon which the circuit is formed.